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1k x 8 dual-port static ram cy7c130/cy7c131 cy7c140/cy7c141 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 document #: 38-06002 rev. *c revised march 7, 2005 features ? true dual-ported memory cells which allow simulta - neous reads of the same memory location ? 1k x 8 organization ? 0.65-micron cmos fo r optimum speed/power ? high-speed access: 15 ns ? low operating power: i cc = 110 ma (max.) ? fully asynchronous operation ? automatic power-down ? master cy7c130/cy7c131 easily expands data bus width to 16 or more bits using slave cy7c140/cy7c141 ? busy output flag on cy7c130/cy7c131; busy input on cy7c140/cy7c141 ? int flag for port-to-p ort communication ? available in 48-pin dip (cy7c130/140), 52-pin plcc, 52-pin pb-free plcc, 52-pin tqfp and 52-pin pb-free tqfp. functional description the cy7c130/cy7c131/cy7c140 and cy7c141 are high-speed cmos 1k by 8 dual-port static rams. two ports are provided permitting independent access to any location in memory. the cy7c130/ cy7c131 can be utilized as either a standalone 8-bit dual-port static ram or as a master dual-port ram in conjunction with the cy7c140/cy7c141 slave dual-port device in systems requ iring 16-bit or greater word widths. it is the solution to applications requiring shared or buffered data, such as cache memory for dsp, bit-slice, or multiprocessor designs. each port has independent control pins; chip enable ( ce ), write enable (r/ w ), and output enable ( oe ). two flags are provided on each port, busy and int . busy signals that the port is trying to access the same location currently being accessed by the other port. int is an interrupt flag indicating that data has been placed in a unique location (3ff for the left port and 3fe for the right por t). an automatic power-down feature is controlled independently on each port by the chip enable ( ce ) pins. the cy7c130 and cy7c140 are available in 48-pin dip. the cy7c131 and cy7c141 are available in 52-pin plcc, 52-pin pb-free plcc, 52-pin pqfp and 52-pin pb-free pqfp. logic block diagram pin configurations 13 14 15 16 17 18 19 20 21 22 23 26 27 28 32 31 30 29 33 36 35 34 24 25 gnd 1 2 3 4 5 6 7 8 9 10 11 38 39 40 44 43 42 41 45 48 47 46 12 37 r/w l ce l busy l int l oe l a 0l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l ce r r/w r busy r int r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r i/o 6r i/o 5r i/o 4r i/o 3r i/o 2r i/o 1r i/o 0r v cc dip top view 7c130 7c140 r/w l busy l ce l oe l a 9l a 0l a 0r a 9r r/w r ce r oe r ce r oe r ce l oe l r/w l r/w r i/o 7l i/o 0l i/o 7r i/o 0r busy r int l int r arbitration logic (7c130/7c131 only) and interrupt logic control i/o control i/o memory array address decoder address decoder [1] [2] [2] note: 1. cy7c130/cy7c131 (master): busy is open drain output and requires pull-up resistor cy7c140/cy7c141 (slave): busy is input. 2. open drain outputs: pull-up resistor required.
pin configuration (continued ) 1 v cc top view plcc oe r a 0r 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd oe busy int a nc r/w ce r/w busy int nc 0l l l l l l ce r r r r 7c131 7c141 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 52 5150 49 48 47 45 44 43 42 41 40 top view pqfp v cc oe busy int a nc r/w ce r/w busy int nc 0l l l l l l ce r r r r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd 7c131 7c141 pin definitions left port right port description ce l ce r chip enable r/ w l r/ w r read/write enable oe l oe r output enable a 0l ?a 11/12l a 0r ?a 11/12r address i/o 0l ?i/o 15/17l i/o 0r ?i/o 15/17r data bus input/output int l int r interrupt flag busy l busy r busy flag v cc power gnd ground selection guide 7c131-15 [ 3 ] 7c141-15 7c131-25 [ 3 ] 7c141-25 7c130-30 7c131-30 7c140-30 7c141-30 7c130-35 7c131-35 7c140-35 7c141-35 7c130-45 7c131-45 7c140-45 7c141-45 7c130-55 7c131-55 7c140-55 7c141-55 unit maximum access time 15 25 30 35 45 55 ns maximum operating current com?l/ind 190 170 170 120 120 110 ma military 170 170 120 maximum standby current com?l/ind 75 65 65 45 45 35 ma military 65 65 45 shaded areas contain preliminary information. note: 3. 15 and 25-ns version available only in plcc/pqfp packages. cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 2 of 19
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 3 of 19 maximum ratings [ 4 ] (above which the useful life may be impaired. for user guide - lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage to ground potential (pin 48 to pin 24) ........................................... ?0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ?0.5v to +7.0v dc input voltage............................................ ?3.5v to +7.0v output current into outputs (low) .............................20 ma static discharge voltage........................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial ?40 c to +85 c 5v 10% military [ 5 ] ?55 c to +125 c 5v 10% electrical characteristics over the operating range [ 6 ] 7c131-15 [ 3 ] 7c141-15 7c130-30 [ 3 ] 7c131-25,30 7c140-30 7c141-25,30 7c130-35,45 7c131-35,45 7c140-35,45 7c141-35,45 7c130-55 7c131-55 7c140-55 7c141-55 parameter description test conditions min. max. min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage i ol = 4.0 ma 0.4 0.4 0.4 0.4 v i ol = 16.0 ma [ 7 ] 0.5 0.5 0.5 0.5 v ih input high voltage 2.2 2.2 2.2 2.2 v v il input low voltage 0.8 0.8 0.8 0.8 v i ix input leakage current gnd < v i < v cc ?5 +5 ?5 +5 ?5 +5 ?5 +5 a i oz output leakage current gnd < v o < v cc , output disabled ?5 +5 ?5 +5 ?5 +5 ?5 +5 a i os output short circuit current [ 8 , 9 ] v cc = max., v out = gnd ?350 ?350 ?350 ?350 ma i cc v cc operating supply current ce = v il , outputs open, f = f max [ 10 ] com?l 190 170 120 110 ma mil 170 120 i sb1 standby current both ports, ttl inputs ce l and ce r > v ih , f = f max [ 10 ] com?l 75 65 45 35 ma mil 65 45 i sb2 standby current one port, ttl inputs ce l or ce r > v ih , active port outputs open, f = f max [ 10 ] com?l 135 115 90 75 ma mil 115 90 i sb3 standby current both ports, cmos inputs both ports ce l and ce r > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0 com?l 15 15 15 15 ma mil 15 15 shaded areas contain preliminary information. note: 4. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 5. t a is the ?instant on? case temperature 6. see the last page of this specificati on for group a subgroup testing information. 7. busy and int pins only. 8. duration of the short circ uit should not exceed 30 seconds. 9. this parameter is guaranteed but not tested. 10. at f=f max , address and data inputs are cycling at the maximum frequency of read cycle of 1/t rc and using ac test waveforms input levels of gnd to 3v.
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 4 of 19 i sb4 standby current one port, cmos inputs one port ce l or ce r > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, active port outputs open, f = f max [ 10 ] com?l 125 105 85 70 ma mil 105 85 capacitance [ 9 ] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 15 pf c out output capacitance 10 pf ac test loads and waveforms 3.0v 5v output r1 893 ? r2 347 ? 30 pf including jigand scope gnd 90% 90% 10% 5ns 5 ns 5v output r1 893 ? r2 347 ? 5pf including jigand scope (a) (b) output 1.40v equivalent to: thvenin equivalent 5v 281 ? 30 pf busy or int busy output load (cy7c130/cy7c131 only) 10% all input pulses 250 ? electrical characteristics over the operating range [6] (continued) 7c131-15 [3] 7c141-15 7c130-30 [3] 7c131-25,30 7c140-30 7c141-25,30 7c130-35,45 7c131-35,45 7c140-35,45 7c141-35,45 7c130-55 7c131-55 7c140-55 7c141-55
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 5 of 19 switching characteristics over the operating range [ 6 , 11 ] 7c131-15 [ 3 ] 7c141-15 7c130-25 [ 3 ] 7c131-25 7c140-25 7c141-25 7c130-30 7c131-30 7c140-30 7c141-30 parameter description min. max. min. max. min. max. unit read cycle t rc read cycle time 15 25 30 ns t aa address to data valid [ 12 ] 15 25 30 ns t oha data hold from address change 0 0 0 ns t ace ce low to data valid [ 12 ] 15 25 30 ns t doe oe low to data valid [ 12 ] 10 15 20 ns t lzoe oe low to low z [ 9 , 13 , 14 ] 3 3 3 ns t hzoe oe high to high z [ 9 , 13 , 14 ] 10 15 15 ns t lzce ce low to low z [ 9 , 13 , 14 ] 3 5 5 ns t hzce ce high to high z [ 9 , 13 , 14 ] 10 15 15 ns t pu ce low to power-up [ 9 ] 0 0 0 ns t pd ce high to power-down [ 9 ] 15 25 25 ns write cycle [ 15 ] t wc write cycle time 15 25 30 ns t sce ce low to write end 12 20 25 ns t aw address set-up to write end 12 20 25 ns t ha address hold from write end 2 2 2 ns t sa address set-up to write start 0 0 0 ns t pwe r/ w pulse width 12 15 25 ns t sd data set-up to write end 10 15 15 ns t hd data hold from write end 0 0 0 ns t hzwe r/ w low to high z [ 14 ] 10 15 15 ns t lzwe r/ w high to low z [ 14 ] 0 0 0 ns shaded area contains preliminary information. note: 11. test conditions assume signal transition times of 5 ns or less , timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading of the specified i ol /i oh, and 30-pf load capacitance. 12. ac test conditions use v oh = 1.6v and v ol = 1.4v. 13. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 14. t lzce , t lzwe , t hzoe , t lzoe , t hzce and t hzwe are tested with c l = 5pf as in part (b) of ac test loads . transition is measured 500 mv from steady state voltage. 15. the internal write time of the memory is defined by the overlap of cs low and r/ w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal that terminate s the write.
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 6 of 19 busy/interrupt timing t bla busy low from address match 15 20 20 ns t bha busy high from address mismatch [ 16 ] 15 20 20 ns t blc busy low from ce low 15 20 20 ns t bhc busy high from ce high [ 16 ] 15 20 20 ns t ps port set up for priority 5 5 5 ns t wb [ 17 ] r/ w low after busy low 0 0 0 ns t wh r/ w high after busy high 13 20 30 ns t bdd busy high to valid data 15 25 30 ns t ddd write data valid to read data valid note 18 note 18 note 18 ns t wdd write pulse to data delay note 18 note 18 note 18 ns interrupt timing t wins r/ w to interrupt set time 15 25 25 ns t eins ce to interrupt set time 15 25 25 ns t ins address to interrupt set time 15 25 25 ns t oinr oe to interrupt reset time [ 16 ] 15 25 25 ns t einr ce to interrupt reset time [ 16 ] 15 25 25 ns t inr address to interrupt reset time [ 16 ] 15 25 25 ns shaded area contains preliminary information. note: 16. these parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 17. cy7c140/cy7c141 only. 18. a write operation on port a, where port a has priority, leaves the data on port b?s outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port b?s address is toggled. ce for port b is toggled. r/ w for port b is toggled during valid read. switching characteristics over the operating range [6,11] (continued) 7c131-15 [3] 7c141-15 7c130-25 [3] 7c131-25 7c140-25 7c141-25 7c130-30 7c131-30 7c140-30 7c141-30 parameter description min. max. min. max. min. max. unit switching characteristics over the operating range [ 6 , 11 ] 7c130-35 7c131-35 7c140-35 7c141-35 7c130-45 7c131-45 7c140-45 7c141-45 7c130-55 7c131-55 7c140-55 7c141-55 parameter description min. max. min. max. min. max. unit read cycle t rc read cycle time 35 45 55 ns t aa address to data valid [ 12 ] 35 45 55 ns t oha data hold from address change 0 0 0 ns t ace ce low to data valid [ 12 ] 35 45 55 ns t doe oe low to data valid [ 12 ] 20 25 25 ns t lzoe oe low to low z [ 9 , 13 , 14 ] 3 3 3 ns t hzoe oe high to high z [ 9 , 13 , 14 ] 20 20 25 ns t lzce ce low to low z [ 9 , 13 , 14 ] 5 5 5 ns
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 7 of 19 t hzce ce high to high z [ 9 , 13 , 14 ] 20 20 25 ns t pu ce low to power-up [ 9 ] 0 0 0 ns t pd ce high to power-down [ 9 ] 35 35 35 ns write cycle [ 15 ] t wc write cycle time 35 45 55 ns t sce ce low to write end 30 35 40 ns t aw address set-up to write end 30 35 40 ns t ha address hold from write end 2 2 2 ns t sa address set-up to write start 0 0 0 ns t pwe r/ w pulse width 25 30 30 ns t sd data set-up to write end 15 20 20 ns t hd data hold from write end 0 0 0 ns t hzwe r/ w low to high z [ 14 ] 20 20 25 ns t lzwe r/ w high to low z [ 14 ] 0 0 0 ns busy/interrupt timing t bla busy low from address match 20 25 30 ns t bha busy high from address mismatch [ 16 ] 20 25 30 ns t blc busy low from ce low 20 25 30 ns t bhc busy high from ce high [ 16 ] 20 25 30 ns t ps port set up for priority 5 5 5 ns t wb [ 17 ] r/ w low after busy low 0 0 0 ns t wh r/ w high after busy high 30 35 35 ns t bdd busy high to valid data 35 45 45 ns t ddd write data valid to read data valid note 18 note 18 note 18 ns t wdd write pulse to data delay note 18 note 18 note 18 ns interrupt timing t wins r/ w to interrupt set time 25 35 45 ns t eins ce to interrupt set time 25 35 45 ns t ins address to interrupt set time 25 35 45 ns t oinr oe to interrupt reset time [ 16 ] 25 35 45 ns t einr ce to interrupt reset time [ 16 ] 25 35 45 ns t inr address to interrupt reset time [ 16 ] 25 35 45 ns switching characteristics over the operating range [6,11] (continued) 7c130-35 7c131-35 7c140-35 7c141-35 7c130-45 7c131-45 7c140-45 7c141-45 7c130-55 7c131-55 7c140-55 7c141-55 parameter description min. max. min. max. min. max. unit
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 8 of 19 switching waveforms read cycle no. 1 [ 19 , 20 ] t rc t aa t oha data valid previous data valid data out address either port address access read cycle no. 2 [ 19 , 21 ] t ace t lzoe t doe t hzoe t hzce data valid data out ce oe t lzce t pu i cc i sb t pd either port ce /oe access read cycle no. 3 [ 20 ] t bha t bdd valid t ddd t wdd address match address match r/w r address r d inr address l busy l dout l t ps t bla read with busy , master: cy7c130 and cy7c131 t rc t pwe valid t hd notes: 19. r/ w is high for read cycle. 20. device is continuously selected, ce = v il and oe = v il . 21. address valid prior to or coincident with ce transition low.
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 9 of 19 write cycle no. 1 (oe three-states data i/os?either port [ 15 , 22 ] t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha ce r/w address t hzoe oe d out data in either port write cycle no. 2 (r/ w three-states data i/os?either port) [ 16 , 23 ] t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance data valid t lzwe address ce r/w data out data in notes: 22. if oe is low during a r/ w controlled write cycle, the write pu lse width must be the larger of t pwe or t hzwe + t sd to allow the data i/o pins to enter high impedance and for data to be placed on the bus for the required t sd . 23. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. switching waveforms (continued)
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 10 of 19 busy timing diagram no. 1 ( ce arbitration) address match t ps ce l valid first: t blc t bhc address match t ps t blc t bhc address l,r busy r ce l ce r busy l ce r ce l address l,r ce r valid first: busy timing diagram no. 2 (address arbitration) left address valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: switching waveforms (continued)
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 11 of 19 busy timing diagram no. 3 t pwe t wb t wh write with busy (slave:cy7c140/cy7c141) busy r/w ce switching waveforms (continued)
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 12 of 19 interrupt timing diagrams write 3ff t ins t wc t eins right side clears int r t ha t sa t wins read 3ff t rc t einr t ha t int t oinr write 3fe t ins t wc t eins t ha t sa t wins right side sets int l left side sets int r left side clears int l read 3fe t einr t ha t inr t oinr t rc addr r ce l r/w l int l oe l addr r r/w r ce r int l addr r ce r r/w r int r oe r addr l r/w l ce l int r switching waveforms (continued)
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 13 of 19 typical dc and ac characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 -55 25 125 1.2 1.0 120 100 80 60 40 20 0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs.supplyvoltage normalized supply current vs. ambient temperature ambient temperature ( c) output voltage (v) output source current vs. output voltage 0.0 0.8 0.8 0.6 0.6 normalized i, i cc v cc =5.0v v in =5.0v v cc =5.0v t a =25 c 0 i cc i cc 1.6 1.4 1.2 1.0 0.8 -55 125 normalized t aa normalized access time vs. ambient temperature ambient temperature ( c) 1.4 1.3 1.2 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supplyvoltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs.output voltage v cc =5.0v t a =25 c 0.6 0.8 v cc =5.0v t a =25 c 1.25 1.0 0.75 10 40 normalized i cc 0.50 normalized i cc vs.cycletime cycle frequency (mhz) 3.0 2.5 2.0 1.5 0.5 0 1.0 2.0 3.0 5.0 normalized t pc 25.0 30.0 20.0 10.0 5.0 0 200 400 600 800 delta t (ns) 0 15.0 0.0 supplyvoltage (v) typical power -on current vs. supply voltage capacitance (pf) typical access time change vs. output loading 4.0 1000 1.0 aa 20 30 0.2 0.6 1.2 i sb3 sb 0.2 0.4 i sb3 25 1.1 v cc =4.5v t a =25 c v cc =4.5v t a =25 c v in =0.5v normalized i, i cc sb
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 14 of 19 ordering information speed (ns) ordering code package name package type operating range 30 cy7c130-30pc p25 48-lead (600-mil) molded dip commercial cy7c130-30pi p25 48-lead (600-mil) molded dip industrial 35 cy7c130-35pc p25 48-lead (600-mil) molded dip commercial cy7c130-35pi p25 48-lead (600-mil) molded dip industrial cy7c130-35dmb d26 48-lead (600-mil) sidebraze dip military 45 cy7c130-45pc p25 48-lead (600-mil) molded dip commercial cy7c130-45pi p25 48-lead (600-mil) molded dip industrial cy7c130-45dmb d26 48-lead (600-mil) sidebraze dip military 55 cy7c130-55pc p25 48-lead (600-mil) molded dip commercial cy7c130-55pi p25 48-lead (600-mil) molded dip industrial cy7c130-55dmb d26 48-lead (600-mil) sidebraze dip military 15 cy7c131-15jc j69 52-lead plastic leaded chip carrier commercial cy7c131-15jxc j69 52-lead lead-free plastic leaded chip carrier cy7c131-15nc n52 52-pin plastic quad flatpack 25 cy7c131-25jc j69 52-lead plastic leaded chip carrier commercial cy7c131-25jxc j69 52-lead lead-free plastic leaded chip carrier cy7c131-25nc n52 52-pin plastic quad flatpack cy7c131-25nxc n52 52-pin lead-free plastic quad flatpack cy7c131-25ji j69 52-lead plastic leaded chip carrier industrial cy7c131-25ni n52 52-pin plastic quad flatpack 30 cy7c131-30jc j69 52-lead plastic leaded chip carrier commercial cy7c131-30nc n52 52-pin plastic quad flatpack cy7c131-30ji j69 52-lead plastic leaded chip carrier industrial 35 cy7c131-35jc j69 52-lead plastic leaded chip carrier commercial cy7c131-35nc n52 52-pin plastic quad flatpack cy7c131-35ji j69 52-lead plastic leaded chip carrier industrial cy7c131-35ni n52 52-pin plastic quad flatpack 45 cy7c131-45jc j69 52-lead plastic leaded chip carrier commercial cy7c131-45nc n52 52-pin plastic quad flatpack cy7c131-45ji j69 52-lead plastic leaded chip carrier industrial cy7c131-45ni n52 52-pin plastic quad flatpack 55 cy7c131-55jc j69 52-lead plastic leaded chip carrier commercial cy7c131-55jxc j69 52-lead lead-free plastic leaded chip carrier cy7c131-55nc n52 52-pin plastic quad flatpack cy7c131-55nxc n52 52-pin lead-free plastic quad flatpack cy7c131-55ji j69 52-lead plastic leaded chip carrier industrial cy7c131-55jxi j69 52-lead lead-free plastic leaded chip carrier cy7c131-55ni n52 52-pin plastic quad flatpack shaded areas contain preliminary information.
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 15 of 19 30 cy7c140-30pc p25 48-lead (600-mil) molded dip commercial cy7c140-30pi p25 48-lead (600-mil) molded dip industrial 35 cy7c140-35pc p25 48-lead (600-mil) molded dip commercial cy7c140-35pi p25 48-lead (600-mil) molded dip industrial cy7c140-35dmb d26 48-lead (600-mil) sidebraze dip military 45 cy7c140-45pc p25 48-lead (600-mil) molded dip commercial cy7c140-45pi p25 48-lead (600-mil) molded dip industrial cy7c140-45dmb d26 48-lead (600-mil) sidebraze dip military 55 cy7c140-55pc p25 48-lead (600-mil) molded dip commercial cy7c140-55pi p25 48-lead (600-mil) molded dip industrial cy7c140-55dmb d26 48-lead (600-mil) sidebraze dip military 15 cy7c141-15jc j69 52-lead plastic leaded chip carrier commercial cy7c141-15nc n52 52-pin plastic quad flatpack 25 cy7c141-25jc j69 52-lead plastic leaded chip carrier commercial cy7c141-25jxc j69 52-lead lead-free plastic leaded chip carrier cy7c141-25nc n52 52-pin plastic quad flatpack cy7c141-25ji j69 52-lead plastic leaded chip carrier industrial cy7c141-25ni n52 52-pin plastic quad flatpack 30 cy7c141-30jc j69 52-lead plastic leaded chip carrier commercial cy7c141-30nc n52 52-pin plastic quad flatpack cy7c141-30ji j69 52-lead plastic leaded chip carrier industrial 35 cy7c141-35jc j69 52-lead plastic leaded chip carrier commercial cy7c141-35nc n52 52-pin plastic quad flatpack cy7c141-35ji j69 52-lead plastic leaded chip carrier industrial cy7c141-35ni n52 52-pin plastic quad flatpack 45 cy7c141-45jc j69 52-lead plastic leaded chip carrier commercial cy7c141-45nc n52 52-pin plastic quad flatpack cy7c141-45ji j69 52-lead plastic leaded chip carrier industrial cy7c141-45ni n52 52-pin plastic quad flatpack 55 cy7c141-55jc j69 52-lead plastic leaded chip carrier commercial cy7c141-55nc n52 52-pin plastic quad flatpack cy7c141-55ji j69 52-lead plastic leaded chip carrier industrial cy7c141-55ni n52 52-pin plastic quad flatpack ordering information (continued) speed (ns) ordering code package name package type operating range
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 16 of 19 military specifications group a subgroup testing dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il max. 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 i sb1 1, 2, 3 i sb2 1, 2, 3 i sb3 1, 2, 3 i sb4 1, 2, 3 switching characteristics parameter subgroups read cycle t rc 7, 8, 9, 10, 11 t aa 7, 8, 9, 10, 11 t ace 7, 8, 9, 10, 11 t doe 7, 8, 9, 10, 11 write cycle t wc 7, 8, 9, 10, 11 t sce 7, 8, 9, 10, 11 t aw 7, 8, 9, 10, 11 t ha 7, 8, 9, 10, 11 t sa 7, 8, 9, 10, 11 t pwe 7, 8, 9, 10, 11 t sd 7, 8, 9, 10, 11 t hd 7, 8, 9, 10, 11 busy/interrupt timing t bla 7, 8, 9, 10, 11 t bha 7, 8, 9, 10, 11 t blc 7, 8, 9, 10, 11 t bhc 7, 8, 9, 10, 11 t ps 7, 8, 9, 10, 11 t wins 7, 8, 9, 10, 11 t eins 7, 8, 9, 10, 11 t ins 7, 8, 9, 10, 11 t oinr 7, 8, 9, 10, 11 t einr 7, 8, 9, 10, 11 t inr 7, 8, 9, 10, 11 busy timing t wb [ 24 ] 7, 8, 9, 10, 11 t wh 7, 8, 9, 10, 11 t bdd 7, 8, 9, 10, 11 note: 24. cy7c140/cy7c141 only.
cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 17 of 19 package diagrams 48-lead (600-mil) sidebraze dip d26 mil-std-1835 d-14 config. c 51-80044 ** dimensions in inches min. max. 0.045 0.055 0.020 min. 0.090 0.165 0.023 0.033 0.013 0 .785 0 .795 0.750 0.756 0.756 0.750 0.795 0.785 0.130 0.200 0.021 0.690 0.730 47 7 21 33 34 46 20 8 0.004 seating plane 1 pin #1 id 52-lead plastic leaded chip carrier j69 51-85004-*a 52-lead pb-free plastic leaded chip carrier j69 plastic leaded
51-85020-*a 48-lead (600-mil) molded dip p25 52-lead plastic quad flatpack n52 51-85042-** 52-lead pb-free plastic quad flatpack n52 52-lead plastic quad flatpack n52 cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 18 of 19 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams (continued)
document title: cy7c130/cy7c131/cy7c140/cy7c141 1k x 8 dual-port static ram document number: 38-06002 rev. ecn no. issue date orig. of change description of change ** 110169 09/29/01 szv change from spec number: 38-00027 to 38-06002 *a 122255 12/26/02 rbi power up requirements added to maximum ratings information *b 236751 see ecn ydt removed cross information from features section *c 325936 see ecn ruy added pin definitions table, 52-pin pqfp package diagram and pb-free information cy7c130/cy7c131 cy7c140/cy7c141 document #: 38-06002 rev. *c page 19 of 19 document history page

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